System Functional Test

System functional test is the process of validating that an electronic system functions correctly; it is often performed at the board level. As components become smaller and faster and particularly if stacked chip configurations are used, it becomes more difficult to test them. For example, conventional connectors and cables may be physically too large to provide a sufficient number of test points, while providing adequate signaling speed.

Accordingly, many manufacturers are gradually transferring test capabilities from external test boxes to test circuits that are permanently resident in the system. Boundary scan tests based on the IEEE 1149.1 standard have been used extensively, and will continue to be useful for many years to come. However, a new test method promises higher confidence in system level performance, and at a lower test cost. The method employs parallel sampling and comparing of system bus data during selected system cycles. This is a general approach that can be applied to any electronic system employing a microprocessor and a parallel system bus.

A preferred embodiment is described wherein the system is running in its native mode. That is, the system is performing a suite of normal functions, running under system software that may be programmed in C or Java or any other high level language, and its behavior is verified by examination of activity on its parallel system bus. The bus is sampled in real time, without interrupting the normal processing flow. The key to this solution is providing a resident test chip as part of the system; the test chip is interfaced to an external test support computer during the validation procedure. Adding the test chip increases the bill of materials cost but greatly simplifies the validation task, and results in more reliable and maintainable systems.

A continuation of this patent has been applied for. It includes claims relating to a powerful new method for learning correct system behavior: statistical evaluation of multiple prototype parts. These parts may be on the the first wafer produced. The continuation also includes claims relating to the test chip by itself.

Even the most densely packed systems can be validated at full power and full speed, and the test programs can be developed quickly. This can enable test capability to maintain pace with the rapid evolution in packaging technology, see the graphic below. For more details, please refer to the patent.

 

 

 

 

 

 

 

 

 

 

 

Packaging innovations may include increased levels of miniaturization, higher speeds, stacked arrangements that can include through silicon vias (TSVs), greater use of bare die, embedded passives, tight integration of heterogeneous components such as digital and RF, and new cooling methods.